1. Field of the Invention
This invention relates to a method of detachable direct bonding at low temperatures used for thin wafer or die layer transfer and the application of such techniques in materials, devices, and 3-D (three-dimensional) device integration.
2. Background of the Invention
As the scaling limits of the conventional bulk silicon device are approaching, there is a strong demand to monolithically combine a variety of materials to form integrated materials for integrated circuits (ICs) with enhanced performances. For system-on-a chip (SOC) preparation, a variety of functions are required on a chip. Many functions are usually best made from their respective materials other than silicon. Therefore, integrated materials that combine thin films of dissimilar materials on a single wafer are highly desirable. Wafer or die direct bonding is one technology to achieve this goal. Usually, wafers or dies with thickness that are sufficient for handling are bonded at room temperature followed by annealing at elevated temperatures to enhance the bond. In order to bond dissimilar materials having different thermal expansion coefficients, low temperature bonding is utilized. Low temperature bonding is also crucial for materials having a low decomposition temperature or for materials that are temperature sensitive even though such materials can be thermally matched.
Moreover, wafers or dies of dissimilar materials that are bonded to the host substrate are preferably thinned to a thickness that is less than a critical value for the respective materials combination to avoid generation of misfit dislocations in the layer and to prevent sliding or cracking of the bonded pair during subsequent thermal processing steps. Transfer of dissimilar layers of different types onto a host wafer can be accomplished for example by the following steps: (1) bond a full thickness wafer or dies to a carrier substrate, (2) thin the bonded wafer or dies by grinding, CMP (chemo-mechanical polishing), etching or splitting, (3) subsequently bond the thinned wafer or dies which are bonded to the carrier substrate to a host wafer, and then (4) remove the carrier substrate.
Design of processes needed to produce different functions on the same chip of integrated materials can be difficult and hard to optimize. Also, resultant SOC chips may get too large, leading to a low yield. Therefore, one alternative approach is to interconnect different IC layers that are fully processed and tested to form stacking ICs or three-dimensional system-on-a chip (3-D SOC) by wafer bonding and layer transfer. Ramm et al in U.S. Pat. No. 5,563,684, the entire contents of which are incorporated by reference, describe such integration. Since wafer direct bonding and layer transfer is Very Large Scale Integration (VLSI) compatible, flexible and manufacturable technology, using direct bonding to form 3-D SOC is highly favorable to other bonding methods such as adhesive bonding or anodic bonding. The 3-D SOC approach is also complementary to the materials integration method because the processed functional layers can be considered as unique dissimilar materials layers. In many cases it is desirable that the thin device dies that are transferred onto a host wafer are top-up. This can be realized by the layer transfer procedures mentioned above.
Transfer of a device layer from its host substrate to a desired substrate can significantly improve device performance. Workers in the field have shown that, by device layer transfer from its host silicon wafer to a glass substrate, an ultra low power RF bipolar IC was realized. Furthermore, the transfer of a power device layer from a host silicon wafer to a highly thermally conductive substrate is expected significantly increase device power capability. In general, device layer transfer provides opportunities for device performance enhancement.
Traditionally, mechanical grinding, polishing or selective etching are employed to remove the handle substrate in the final step of the layer transfer procedures mentioned above. However, these methods are time consuming, environmentally unfriendly and result in a low thickness uniformity of the remaining layer. A detachable bonding technology that can separate the carrier wafer itself at step (4) is desired. A few methods of detachable bonding methods have been suggested; such as for example water-enhanced de-bonding, gas or water jet de-bonding, using a water-soluble or solvent-soluble adhesive bonding layer, wax bonding, plasma removal of a polyimide bonding layer, and laser ablation of polymeric adhesive bonding layer or a hydrogenated amorphous silicon (a-Si:H) bonding layer. These methods have drawbacks.
In water-enhanced de-bonding, the bonding energy of the bonded wafers has to be very low (˜100 mJ/m2) and therefore, is not sufficient for the layer transfer process steps. The low bonding energy makes water-enhanced de-bonding useful only for wafer surface protection by wafer bonding. In gas or water-jet debonding, in order to avoid damaging the separated wafer surfaces, the bonding energy of the bonded pairs is limited to below 750 mJ/m2 and practically can only work at a wafer level. Meanwhile, water or solvent debonding is based on water- or solvent-soluble adhesive bonding technologies that are suspect if a strong, reliable and uniform bonds are needed. Water or solvent-de-bonding also relies on the lateral reaction between the water or solvent and the adhesive bonding layer at the bonding interface is time consuming and limits the size of the bonded pairs.
For wax bonding, Apiezon® wax is employed as either the substrate itself or a bonding layer. For the latter, wax bonding has similar problems as in water-soluble bonding. For the former, Apiezon wax is not strong enough for processes in a layer transfer procedure. Plasma removal of a polyimide bonding layer is similar to the water soluble process except the plasma removal is a dry process. In laser ablation, the carrier wafer must be transparent to the incident laser such as a glass wafer. This method requires ablation of the polymer layer or the a-Si:H layer at the film/substrate interface, and is based on the explosive release and accumulation of gas from the film/substrate interface. Exciter laser pulses with energy >400 mJ/cm2 are required.
Hence, prior art techniques for bonding and release present numerous drawbacks and disadvantages.